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Cantidad | Precio (sin IVA) |
---|---|
1+ | 0,909 € |
10+ | 0,653 € |
100+ | 0,519 € |
Información del producto
Resumen del producto
The CD74HC73M is a high speed CMOS dual negative-edge-triggered J-K Flip-flop with reset. It utilizes silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads It has independent J, K, Reset and Clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC107 but differs in terminal assignment and in some parametric limits.
- Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
- Asynchronous reset
- Complementary outputs
- Buffered inputs
- Balanced propagation delay and transition times
- Significant power reduction compared to LSTTL logic ICs
- High noise immunity
- Direct LSTTL input logic compatibility
- CMOS Input compatibility
- 10 LSTTL Load standard outputs
- 15 LSTTL Load bus driver outputs
- Green product and no Sb/Br
Especificaciones técnicas
74HC73
13ns
5.2mA
SOIC
Flanco Negativo
2V
74HC
-55°C
-
MSL 1 - Ilimitado
D
60MHz
SOIC
14Pins
Complementaria
6V
7473
125°C
-
No SVHC (27-Jun-2018)
Documentos técnicos (2)
Legislación y medioambiente
País donde se realizó la mayor parte del proceso de producciónPaís de origen:Malaysia
País donde se realizó la mayor parte del proceso de producción
RoHS
RoHS
Certificado de conformidad del producto